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FPGAs: A Way Forward For Networking Silicon?

679 Words. Plan about 4 minute(s) to read this.

I’ve become somewhat fascinated with the silicon that moves packets around our networks. My knowledge is admittedly shallow on the topic. That said, I believe I can make the following generalizations about the 3 major kinds of networking silicon to be found on the market today.

1. X86. General purpose CPUs are not especially well suited to moving packets around, which isn’t to say there’s some adequate-for-their-purpose performance coming out of hypervisor vSwitches. But we’re talking tens of gigabits. Not hundreds. That said, x86 is the most flexible in terms of programming. Therefore, vSwitches in hypervisors might end up with the ability to do new encapsulations or execute new forwarding paradigms before that same function can be done in dedicated network silicon. Thus, we’ll see the proposed Geneve overlay running in a vSwitch before we see it in a hardware switch, if we ever do. By the same token, we also see the latest OpenFlow specifications making their way into Open vSwitch (OVS) before we see hardware vendors implementing them.

2. ASICs. Custom designed silicon built expressly for the purpose of forwarding specific network frames and packets across the wire at line rate offer the greatest performance, but the least amount of flexibility. ASICs are hard for manufacturers to make; they take roughly 1.5-3+ years to design & fabricate, and incur a significant up-front cost. Choosing what features to put into an ASIC requires the foresight of Nostradamus coupled with a gambling man’s nerves of steel. Listen to the Packet Pushers Podcast #185 for more discussion on this interesting topic. The key to understand is that an ASIC, once built, is stuck with the features built into it. This is why it’s not possible to, for example, run a code upgrade to gain TRILL functionality on an ASIC that was never designed to do TRILL encaps. Or why VTEP is not a pervasive feature in data center class switches yet. If no one saw the VXLAN storm coming or wasn’t confident that VXLAN would be a winner, then the ASICs to support VTEP weren’t being spun up.

3. FPGAs. Field programmable gate arrays promise the performance of an ASIC with the programmability of X86. That said, I understand FPGAs to be even harder for manufacturers to create than ASICs and somewhat error-prone to actually program and deliver new functionality on. So yes, FPGAs seem to hit a sweetspot, but might not be so wonderful in real-life networks. Even so, some manufacturers are making FPGAs and putting them into their networking products.

Huawei is one such manufacturer of FPGA-based network processors. Huawei has created the Ethernet Network Processor, which is available in their S12700 switch, and will eventually be found in other switches in the Huawei lineup.

Huawei S12700 series agile switches are core switches designed for next-generation campus networks. Using a fully programmable switching architecture, the S12700 series allows fast, flexible function customization and supports a smooth evolution to software-defined networking (SDN). The S12700 series uses Huawei Ethernet Network Processor (ENP) and provides native wireless access controller (AC) to help build a wired and wireless converged network.

huawei-s12700The big idea behind the ENP is that whatever comes down the line in the form of, say, OpenFlow enhancements or new encapsulation types, the ENP can be programmed to handle it. An FPGA is, theoretically, future proof. That’s a very compelling idea in a networked world that keeps changing. Chip programmability takes the Nostradamus element out of the chip design equation, although certainly places a major burden back on the shoulders of vendors’ development teams.

Are FPGAs a way forward for networking silicon, then? I believe they are an option, but the key is in execution. FPGAs are not new; I remember tracking Xilinx back in college many years ago. If FPGAs were easy, all manufacturers would be making them, and we networking practitioners would be consuming them instead of ASICs. Yet, ASICs dominate. I assume that’s because doing FPGAs right is hard, despite the strong desire for programmability in an unpredictable network world.

Anyone well-versed on ASICs vs. FPGAs care to comment? Feel free below.